The present invention relates generally to microelectromechanical (MEM) structures and methods for fabricating them.
Micromachining is a recent technology for fabricating micromechanical moving structures. In general, semiconductor batch fabrication techniques are employed to achieve what is in effect threedimensional machining of single-crystal and polycrystalline silicon and silicon dielectrics and multiple metal layers, producing such structures as micromotors and microsensors. Thus, except for selective deposition and removal of materials on a substrate, conventional assembly operations are not involved. By way of example, a microsensor is disclosed in Haritonidis et al. U.S. Pat. No. 4,896,098; and an electrostatic micromotor is disclosed in Howe et al. U.S. Pat. Nos. 4,943,750 and 4,997,521.
Conventional machining is impractical for expeditiously fabricating a multiple contact switch system which has submillimeter features because machine tools are limited to larger dimensions and are slow because they operate sequentially. Silicon microelectromechanical (MEM) switch structures are somewhat limited as they must be manufactured, diced into individual switch structures, and then placed into the circuit. Conventional MEMs structures cannot be co-fabricated with hybrid and HDI circuitry due to the unique processing requirements of Si based MEMs devices.
Whereas conventional Si based MEMS structures utilize the differential expansion co-efficient of the silicon, silicon dielectric and metallic layers, the use of shape metal alloy (SMA) in a MEMs structure results in a higher specific work output due to the SMA transition effect. SMAs are typically annealed alloys of primarily titanium and nickel that undergo a predictable phase change at a transition temperature. During this transition the SMA material experiences a large change in dimensions that can be used in actuators for valves and the like see Johnson et al., U.S. Pat. No. 5,325,880. Typical thin films of SMA materials are formed using sputtering techniques to deposit layers ranging from 2000 angstroms to 125 microns. These sputtered films are generally polycrystalline and require heat treatment (annealing) in an oxygen free environment, cold working or a combination to produce the crystalline phase used in MEMs devices. Purely thermal annealing can require temperatures on the order of 500.degree. C.
Also related to the invention is what is known as high density interconnect (HDI) technology for multi-chip module packaging, such as is disclosed in Eichelberger et al. U.S. Pat. No.4,783,695. Very briefly, in systems employing this high density interconnect structure, various components, such as semiconductor integrated circuit chips, are placed within cavities formed in a ceramic substrate. A multi-layer overcoat structure is then built up to electrically interconnect the components into an actual functioning system. To begin the multi-layer overcoat structure, a polyimide dielectric film, such as KAPTON.TM. polyimide (available from E. I. Dupont de Nemours & Company, Wilmington, Del.), about 0.5 to 3 mils (12.7 to 76 microns) thick, is laminated across the top of the chips, other components and the substrate, employing ULTEM.TM. polyetherimide resin (available from General Electric Company, Pittsfield, Mass.) or other adhesives. The actual as-placed locations of the various components and contact pads thereon are determined by optical sighting, and via holes are adaptively laser drilled in the KAPTON.TM. film and adhesive layers in alignment with the contact pads on the electronic components. Exemplary laser drilling techniques are disclosed in Eichelberger et al.
U.S. Pat. Nos. 4,714,516 and 4,894,115; and in Loughran et al. U.S. Pat. No. 4,764,485. Such HDI vias are typically on the order of one to two mils (25 to 50 microns) in diameter. A metallization layer is deposited over the KAPTON.TM. film layer and extends into the via holes to make electrical contact to chip contact pads. This metallization layer may be patterned to form individual conductors during its deposition process, or it may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser which is scanned relative to the substrate to provide an accurately aligned conductor pattern upon completion of the process. Exemplary techniques for patterning the metallization layer are disclosed in Wojnarowski et al. U.S. Pat. Nos. 4,780,177 and 4,842,677; and in Eichelberger et al. U.S. Pat. No.4,835,704 which discloses an "Adaptive Lithography System to Provide High Density Interconnect." Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system as disclosed in aforementioned U.S. Pat. No. 4,835,704. Additional dielectric and metallization layers are provided as required in order to make all of the desired electrical connections among the chips. This process of metal patterning on polymers, lamination, via drilling and additional metal deposition and patterning can be used to fabricate free standing precision flexible circuits, back plane assemblies and the like when the first polymer layer is not laminated over a substrate containing semiconductor die as described Eichelberger et al U.S. Pat. No. 5,452,182"Flexible HDI structure and Flexibly Interconnected System".